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    <h1>File: /Users/paulross/dev/linux/linux-3.13/arch/x86/include/asm/barrier.h</h1>
    <p>Green shading in the line number column
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    <pre><a name="1" /><span class="True">       1:</span> <span class="f">#</span><span class="n">ifndef</span> <a href="cpu.c_macros_noref.html#_X0FTTV9YODZfQkFSUklFUl9IXzA_"><span class="b">_ASM_X86_BARRIER_H</span></a>
<a name="2" /><span class="True">       2:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_X0FTTV9YODZfQkFSUklFUl9IXzA_"><span class="b">_ASM_X86_BARRIER_H</span></a>
<a name="3" /><span class="True">       3:</span> 
<a name="4" /><span class="True">       4:</span> <span class="f">#</span><span class="n">include</span> <span class="f">&lt;</span><span class="m">asm</span><span class="f">/</span><a href="cpu.c_macros_ref.html#_YWx0ZXJuYXRpdmVfMA__"><span class="b">alternative</span></a><span class="f">.</span><span class="b">h</span><span class="f">&gt;</span>
<a name="5" /><span class="True">       5:</span> <span class="f">#</span><span class="n">include</span> <span class="f">&lt;</span><span class="m">asm</span><span class="f">/</span><span class="b">nops</span><span class="f">.</span><span class="b">h</span><span class="f">&gt;</span>
<a name="6" /><span class="True">       6:</span> 
<a name="7" /><span class="True">       7:</span> <span class="k">/*</span>
<a name="8" /><span class="True">       8:</span> <span class="k"> * Force strict CPU ordering.</span>
<a name="9" /><span class="True">       9:</span> <span class="k"> * And yes, this is required on UP too when we&apos;re talking</span>
<a name="10" /><span class="True">      10:</span> <span class="k"> * to devices.</span>
<a name="11" /><span class="True">      11:</span> <span class="k"> */</span>
<a name="12" /><span class="True">      12:</span> 
<a name="13" /><span class="False">      13:</span> <span class="f">#</span><span class="n">ifdef</span> <span class="b">CONFIG_X86_32</span>
<a name="14" /><span class="False">      14:</span> <span class="k">/*</span>
<a name="15" /><span class="False">      15:</span> <span class="k"> * Some non-Intel clones support out of order store. wmb() ceases to be a</span>
<a name="16" /><span class="False">      16:</span> <span class="k"> * nop for these.</span>
<a name="17" /><span class="False">      17:</span> <span class="k"> */</span>
<a name="18" /><span class="False">      18:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_bWJfMA__"><span class="b">mb</span></a><span class="f">(</span><span class="f">)</span> <a href="cpu.c_macros_ref.html#_YWx0ZXJuYXRpdmVfMA__"><span class="b">alternative</span></a><span class="f">(</span><span class="e">&quot;lock; addl $0,0(%%esp)&quot;</span><span class="f">,</span> <span class="e">&quot;mfence&quot;</span><span class="f">,</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfWE1NMl8w"><span class="b">X86_FEATURE_XMM2</span></a><span class="f">)</span>
<a name="19" /><span class="False">      19:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_cm1iXzA_"><span class="b">rmb</span></a><span class="f">(</span><span class="f">)</span> <a href="cpu.c_macros_ref.html#_YWx0ZXJuYXRpdmVfMA__"><span class="b">alternative</span></a><span class="f">(</span><span class="e">&quot;lock; addl $0,0(%%esp)&quot;</span><span class="f">,</span> <span class="e">&quot;lfence&quot;</span><span class="f">,</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfWE1NMl8w"><span class="b">X86_FEATURE_XMM2</span></a><span class="f">)</span>
<a name="20" /><span class="False">      20:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_d21iXzA_"><span class="b">wmb</span></a><span class="f">(</span><span class="f">)</span> <a href="cpu.c_macros_ref.html#_YWx0ZXJuYXRpdmVfMA__"><span class="b">alternative</span></a><span class="f">(</span><span class="e">&quot;lock; addl $0,0(%%esp)&quot;</span><span class="f">,</span> <span class="e">&quot;sfence&quot;</span><span class="f">,</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfWE1NXzA_"><span class="b">X86_FEATURE_XMM</span></a><span class="f">)</span>
<a name="21" /><span class="True">      21:</span> <span class="f">#</span><span class="n">else</span>
<a name="22" /><span class="True">      22:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_bWJfMA__"><span class="b">mb</span></a><span class="f">(</span><span class="f">)</span>     <span class="m">asm</span> <span class="m">volatile</span><span class="f">(</span><span class="e">&quot;mfence&quot;</span><span class="f">::</span><span class="f">:</span><span class="e">&quot;memory&quot;</span><span class="f">)</span>
<a name="23" /><span class="True">      23:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_cm1iXzA_"><span class="b">rmb</span></a><span class="f">(</span><span class="f">)</span>    <span class="m">asm</span> <span class="m">volatile</span><span class="f">(</span><span class="e">&quot;lfence&quot;</span><span class="f">::</span><span class="f">:</span><span class="e">&quot;memory&quot;</span><span class="f">)</span>
<a name="24" /><span class="True">      24:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_d21iXzA_"><span class="b">wmb</span></a><span class="f">(</span><span class="f">)</span>    <span class="m">asm</span> <span class="m">volatile</span><span class="f">(</span><span class="e">&quot;sfence&quot;</span> <span class="f">::</span><span class="f">:</span> <span class="e">&quot;memory&quot;</span><span class="f">)</span>
<a name="25" /><span class="True">      25:</span> <span class="f">#</span><span class="n">endif</span>
<a name="26" /><span class="True">      26:</span> 
<a name="27" /><span class="True">      27:</span> <span class="k">/**</span>
<a name="28" /><span class="True">      28:</span> <span class="k"> * read_barrier_depends - Flush all pending reads that subsequents reads</span>
<a name="29" /><span class="True">      29:</span> <span class="k"> * depend on.</span>
<a name="30" /><span class="True">      30:</span> <span class="k"> *</span>
<a name="31" /><span class="True">      31:</span> <span class="k"> * No data-dependent reads from memory-like regions are ever reordered</span>
<a name="32" /><span class="True">      32:</span> <span class="k"> * over this barrier.  All reads preceding this primitive are guaranteed</span>
<a name="33" /><span class="True">      33:</span> <span class="k"> * to access memory (but not necessarily other CPUs&apos; caches) before any</span>
<a name="34" /><span class="True">      34:</span> <span class="k"> * reads following this primitive that depend on the data return by</span>
<a name="35" /><span class="True">      35:</span> <span class="k"> * any of the preceding reads.  This primitive is much lighter weight than</span>
<a name="36" /><span class="True">      36:</span> <span class="k"> * rmb() on most CPUs, and is never heavier weight than is</span>
<a name="37" /><span class="True">      37:</span> <span class="k"> * rmb().</span>
<a name="38" /><span class="True">      38:</span> <span class="k"> *</span>
<a name="39" /><span class="True">      39:</span> <span class="k"> * These ordering constraints are respected by both the local CPU</span>
<a name="40" /><span class="True">      40:</span> <span class="k"> * and the compiler.</span>
<a name="41" /><span class="True">      41:</span> <span class="k"> *</span>
<a name="42" /><span class="True">      42:</span> <span class="k"> * Ordering is not guaranteed by anything other than these primitives,</span>
<a name="43" /><span class="True">      43:</span> <span class="k"> * not even by data dependencies.  See the documentation for</span>
<a name="44" /><span class="True">      44:</span> <span class="k"> * memory_barrier() for examples and URLs to more information.</span>
<a name="45" /><span class="True">      45:</span> <span class="k"> *</span>
<a name="46" /><span class="True">      46:</span> <span class="k"> * For example, the following code would force ordering (the initial</span>
<a name="47" /><span class="True">      47:</span> <span class="k"> * value of &quot;a&quot; is zero, &quot;b&quot; is one, and &quot;p&quot; is &quot;&amp;a&quot;):</span>
<a name="48" /><span class="True">      48:</span> <span class="k"> *</span>
<a name="49" /><span class="True">      49:</span> <span class="k"> * &lt;programlisting&gt;</span>
<a name="50" /><span class="True">      50:</span> <span class="k"> *    CPU 0                CPU 1</span>
<a name="51" /><span class="True">      51:</span> <span class="k"> *</span>
<a name="52" /><span class="True">      52:</span> <span class="k"> *    b = 2;</span>
<a name="53" /><span class="True">      53:</span> <span class="k"> *    memory_barrier();</span>
<a name="54" /><span class="True">      54:</span> <span class="k"> *    p = &amp;b;                q = p;</span>
<a name="55" /><span class="True">      55:</span> <span class="k"> *                    read_barrier_depends();</span>
<a name="56" /><span class="True">      56:</span> <span class="k"> *                    d = *q;</span>
<a name="57" /><span class="True">      57:</span> <span class="k"> * &lt;/programlisting&gt;</span>
<a name="58" /><span class="True">      58:</span> <span class="k"> *</span>
<a name="59" /><span class="True">      59:</span> <span class="k"> * because the read of &quot;*q&quot; depends on the read of &quot;p&quot; and these</span>
<a name="60" /><span class="True">      60:</span> <span class="k"> * two reads are separated by a read_barrier_depends().  However,</span>
<a name="61" /><span class="True">      61:</span> <span class="k"> * the following code, with the same initial values for &quot;a&quot; and &quot;b&quot;:</span>
<a name="62" /><span class="True">      62:</span> <span class="k"> *</span>
<a name="63" /><span class="True">      63:</span> <span class="k"> * &lt;programlisting&gt;</span>
<a name="64" /><span class="True">      64:</span> <span class="k"> *    CPU 0                CPU 1</span>
<a name="65" /><span class="True">      65:</span> <span class="k"> *</span>
<a name="66" /><span class="True">      66:</span> <span class="k"> *    a = 2;</span>
<a name="67" /><span class="True">      67:</span> <span class="k"> *    memory_barrier();</span>
<a name="68" /><span class="True">      68:</span> <span class="k"> *    b = 3;                y = b;</span>
<a name="69" /><span class="True">      69:</span> <span class="k"> *                    read_barrier_depends();</span>
<a name="70" /><span class="True">      70:</span> <span class="k"> *                    x = a;</span>
<a name="71" /><span class="True">      71:</span> <span class="k"> * &lt;/programlisting&gt;</span>
<a name="72" /><span class="True">      72:</span> <span class="k"> *</span>
<a name="73" /><span class="True">      73:</span> <span class="k"> * does not enforce ordering, since there is no data dependency between</span>
<a name="74" /><span class="True">      74:</span> <span class="k"> * the read of &quot;a&quot; and the read of &quot;b&quot;.  Therefore, on some CPUs, such</span>
<a name="75" /><span class="True">      75:</span> <span class="k"> * as Alpha, &quot;y&quot; could be set to 3 and &quot;x&quot; to 0.  Use rmb()</span>
<a name="76" /><span class="True">      76:</span> <span class="k"> * in cases like this where there are no data dependencies.</span>
<a name="77" /><span class="True">      77:</span> <span class="k"> **/</span>
<a name="78" /><span class="True">      78:</span> 
<a name="79" /><span class="True">      79:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_cmVhZF9iYXJyaWVyX2RlcGVuZHNfMA__"><span class="b">read_barrier_depends</span></a><span class="f">(</span><span class="f">)</span>    <span class="m">do</span> <span class="f">{</span> <span class="f">}</span> <span class="m">while</span> <span class="f">(</span><span class="c">0</span><span class="f">)</span>
<a name="80" /><span class="True">      80:</span> 
<a name="81" /><span class="True">      81:</span> <span class="f">#</span><span class="n">ifdef</span> <a href="cpu.c_macros_ref.html#_Q09ORklHX1NNUF8w"><span class="b">CONFIG_SMP</span></a>
<a name="82" /><span class="True">      82:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_c21wX21iXzA_"><span class="b">smp_mb</span></a><span class="f">(</span><span class="f">)</span>    <a href="cpu.c_macros_ref.html#_bWJfMA__"><span class="b">mb</span></a><span class="f">(</span><span class="f">)</span>
<a name="83" /><span class="False">      83:</span> <span class="f">#</span><span class="n">ifdef</span> <span class="b">CONFIG_X86_PPRO_FENCE</span>
<a name="84" /><span class="False">      84:</span> <span class="f">#</span> <span class="n">define</span> <a href="cpu.c_macros_ref.html#_c21wX3JtYl8w"><span class="b">smp_rmb</span></a><span class="f">(</span><span class="f">)</span>    <a href="cpu.c_macros_noref.html#_cm1iXzA_"><span class="b">rmb</span></a><span class="f">(</span><span class="f">)</span>
<a name="85" /><span class="True">      85:</span> <span class="f">#</span><span class="n">else</span>
<a name="86" /><span class="True">      86:</span> <span class="f">#</span> <span class="n">define</span> <a href="cpu.c_macros_ref.html#_c21wX3JtYl8w"><span class="b">smp_rmb</span></a><span class="f">(</span><span class="f">)</span>    <a href="cpu.c_macros_ref.html#_YmFycmllcl8w"><span class="b">barrier</span></a><span class="f">(</span><span class="f">)</span>
<a name="87" /><span class="True">      87:</span> <span class="f">#</span><span class="n">endif</span>
<a name="88" /><span class="False">      88:</span> <span class="f">#</span><span class="n">ifdef</span> <span class="b">CONFIG_X86_OOSTORE</span>
<a name="89" /><span class="False">      89:</span> <span class="f">#</span> <span class="n">define</span> <a href="cpu.c_macros_ref.html#_c21wX3dtYl8w"><span class="b">smp_wmb</span></a><span class="f">(</span><span class="f">)</span>     <a href="cpu.c_macros_noref.html#_d21iXzA_"><span class="b">wmb</span></a><span class="f">(</span><span class="f">)</span>
<a name="90" /><span class="True">      90:</span> <span class="f">#</span><span class="n">else</span>
<a name="91" /><span class="True">      91:</span> <span class="f">#</span> <span class="n">define</span> <a href="cpu.c_macros_ref.html#_c21wX3dtYl8w"><span class="b">smp_wmb</span></a><span class="f">(</span><span class="f">)</span>    <a href="cpu.c_macros_ref.html#_YmFycmllcl8w"><span class="b">barrier</span></a><span class="f">(</span><span class="f">)</span>
<a name="92" /><span class="True">      92:</span> <span class="f">#</span><span class="n">endif</span>
<a name="93" /><span class="True">      93:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_c21wX3JlYWRfYmFycmllcl9kZXBlbmRzXzA_"><span class="b">smp_read_barrier_depends</span></a><span class="f">(</span><span class="f">)</span>    <a href="cpu.c_macros_ref.html#_cmVhZF9iYXJyaWVyX2RlcGVuZHNfMA__"><span class="b">read_barrier_depends</span></a><span class="f">(</span><span class="f">)</span>
<a name="94" /><span class="True">      94:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_c2V0X21iXzA_"><span class="b">set_mb</span></a><span class="f">(</span><span class="b">var</span><span class="f">,</span> <span class="b">value</span><span class="f">)</span> <span class="m">do</span> <span class="f">{</span> <span class="f">(</span><span class="m">void</span><span class="f">)</span><a href="cpu.c_macros_ref.html#_eGNoZ18w"><span class="b">xchg</span></a><span class="f">(</span><span class="f">&amp;</span><span class="b">var</span><span class="f">,</span> <span class="b">value</span><span class="f">)</span><span class="f">;</span> <span class="f">}</span> <span class="m">while</span> <span class="f">(</span><span class="c">0</span><span class="f">)</span>
<a name="95" /><span class="False">      95:</span> <span class="f">#</span><span class="n">else</span>
<a name="96" /><span class="False">      96:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_c21wX21iXzA_"><span class="b">smp_mb</span></a><span class="f">(</span><span class="f">)</span>    <a href="cpu.c_macros_ref.html#_YmFycmllcl8w"><span class="b">barrier</span></a><span class="f">(</span><span class="f">)</span>
<a name="97" /><span class="False">      97:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_c21wX3JtYl8w"><span class="b">smp_rmb</span></a><span class="f">(</span><span class="f">)</span>    <a href="cpu.c_macros_ref.html#_YmFycmllcl8w"><span class="b">barrier</span></a><span class="f">(</span><span class="f">)</span>
<a name="98" /><span class="False">      98:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_c21wX3dtYl8w"><span class="b">smp_wmb</span></a><span class="f">(</span><span class="f">)</span>    <a href="cpu.c_macros_ref.html#_YmFycmllcl8w"><span class="b">barrier</span></a><span class="f">(</span><span class="f">)</span>
<a name="99" /><span class="False">      99:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_c21wX3JlYWRfYmFycmllcl9kZXBlbmRzXzA_"><span class="b">smp_read_barrier_depends</span></a><span class="f">(</span><span class="f">)</span>    <span class="m">do</span> <span class="f">{</span> <span class="f">}</span> <span class="m">while</span> <span class="f">(</span><span class="c">0</span><span class="f">)</span>
<a name="100" /><span class="False">     100:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_c2V0X21iXzA_"><span class="b">set_mb</span></a><span class="f">(</span><span class="b">var</span><span class="f">,</span> <span class="b">value</span><span class="f">)</span> <span class="m">do</span> <span class="f">{</span> <span class="b">var</span> <span class="f">=</span> <span class="b">value</span><span class="f">;</span> <a href="cpu.c_macros_ref.html#_YmFycmllcl8w"><span class="b">barrier</span></a><span class="f">(</span><span class="f">)</span><span class="f">;</span> <span class="f">}</span> <span class="m">while</span> <span class="f">(</span><span class="c">0</span><span class="f">)</span>
<a name="101" /><span class="True">     101:</span> <span class="f">#</span><span class="n">endif</span>
<a name="102" /><span class="True">     102:</span> 
<a name="103" /><span class="True">     103:</span> <span class="k">/*</span>
<a name="104" /><span class="True">     104:</span> <span class="k"> * Stop RDTSC speculation. This is needed when you need to use RDTSC</span>
<a name="105" /><span class="True">     105:</span> <span class="k"> * (or get_cycles or vread that possibly accesses the TSC) in a defined</span>
<a name="106" /><span class="True">     106:</span> <span class="k"> * code region.</span>
<a name="107" /><span class="True">     107:</span> <span class="k"> *</span>
<a name="108" /><span class="True">     108:</span> <span class="k"> * (Could use an alternative three way for this if there was one.)</span>
<a name="109" /><span class="True">     109:</span> <span class="k"> */</span>
<a name="110" /><span class="True">     110:</span> <span class="m">static</span> <a href="cpu.c_macros_ref.html#_X19hbHdheXNfaW5saW5lXzA_"><span class="b">__always_inline</span></a> <span class="m">void</span> <span class="b">rdtsc_barrier</span><span class="f">(</span><span class="m">void</span><span class="f">)</span>
<a name="111" /><span class="True">     111:</span> <span class="f">{</span>
<a name="112" /><span class="True">     112:</span>     <a href="cpu.c_macros_ref.html#_YWx0ZXJuYXRpdmVfMA__"><span class="b">alternative</span></a><span class="f">(</span><a href="cpu.c_macros_ref.html#_QVNNX05PUDNfMA__"><span class="b">ASM_NOP3</span></a><span class="f">,</span> <span class="e">&quot;mfence&quot;</span><span class="f">,</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfTUZFTkNFX1JEVFNDXzA_"><span class="b">X86_FEATURE_MFENCE_RDTSC</span></a><span class="f">)</span><span class="f">;</span>
<a name="113" /><span class="True">     113:</span>     <a href="cpu.c_macros_ref.html#_YWx0ZXJuYXRpdmVfMA__"><span class="b">alternative</span></a><span class="f">(</span><a href="cpu.c_macros_ref.html#_QVNNX05PUDNfMA__"><span class="b">ASM_NOP3</span></a><span class="f">,</span> <span class="e">&quot;lfence&quot;</span><span class="f">,</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfTEZFTkNFX1JEVFNDXzA_"><span class="b">X86_FEATURE_LFENCE_RDTSC</span></a><span class="f">)</span><span class="f">;</span>
<a name="114" /><span class="True">     114:</span> <span class="f">}</span>
<a name="115" /><span class="True">     115:</span> 
<a name="116" /><span class="True">     116:</span> <span class="f">#</span><span class="n">endif</span> <span class="k">/* _ASM_X86_BARRIER_H */</span>
<a name="117" /><span class="True">     117:</span> </pre>
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